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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Table 2-7. RESET, Interrupts, and JTAG Terminal Functions (continued)
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SIGNAL
NAME
NO.
TYPE (1)
(2)
OTHER (3)
(4)
DESCRIPTION
Emulator 0 pin. When TRST is driven low and then high, the state of
the EMU0 pin is latched and used to connect the JTAG pins (TCK,
TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when
the latched value of EMU0 = 0) or t o the DSP Emulation TAP (when the
latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an
interrupt to or from the emulator system and is defined as input/output
IPU
by way of the emulation logic.
EMU0
L6
I/O/Z
DV DDIO
BH
An external pullup to DV DDIO is required to provide a signal rise time of
less than 10 μ sec. A 4.7-k ? resistor is suggested for most applications.
For board design guidelines related to the emulation header, see the
XDS560 Emulator Technical Reference (literature number: SPRU589 ).
The IPU resistor on this pin can be enabled or disabled via the
PDINHIBR2 register.
EXTERNAL INTERRUPTS
IPU
External interrupt inputs (INT1 and INT0). These pins are maskable via
INT1
E7
I
DV DDIO
their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt
BH
IPU
mode bit. The pins can be polled and reset by their specific Interrupt
Flag Register (IFR1, IFR0).
INT0
C6
I
DV DDIO
The IPU resistor on these pins can be enabled or disabled via the
BH
PDINHIBR2 register.
20
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